PCIe Protocol Verification Engineer
Project description
We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way.
Responsibilities
- - Perform functional and compliance verification of PCIe-based SystemC IPs and subsystems. - Integrate SystemC PCIe IP/Subsystem in Avery PCIe VIPs and utilize for protocol-level verification. - Debug complex issues across transaction, data link, and physical layers of PCIe. - Analyze and interpret PCIe specifications for test planning and coverage. - Work closely with design, architecture, and validation teams to ensure feature completeness and spec compliance. - Generate and review verification plans, test reports, and coverage metrics.
SKILLS
Must have
- - 5+ years of experience. - Strong hands-on experience with Avery PCIe VIP (integration, debug, customization). - In-depth knowledge of PCIe protocol (Gen4/Gen5 or higher). - Solid experience in SystemVerilog / UVM methodology. - Strong debug and problem-solving skills using simulators like Questa, VCS, or Xcelium. - Familiarity with coverage-driven verification and constraint random testing. - Good understanding of verification flow, regression setup, and scripting (Python/Perl/Shell). - Excellent communication skills and ability to work independently in a fast-paced environment.
Nice to have
B.E/M.E/M.Tech or B.S/M.S in EE/CE
